1. Field of the Invention
The present invention relates to a digital transmission system for sampling, coding and transmitting an analog signal, and more particularly, to a method and system for controlling reproduction of a sampling clock signal in the digital transmission system in which the sampling clock signal is independent of a transmission path clock signal.
2. Description of Related Art
There is a case where a sampling signal is independent of a transmission path clock signal on a digital transmission path when an analog signal is converted into a digital signal to be transmitted onto the digital transmission path. For example, in digital transmission of a television signal, a sampling signal for the television signal is often determined to be synchronous with a sync signal inherent to the television signal. In a case of a color television signal, the sampling signal is selected to have the frequency more than that of a color subcarrier signal three or four times. On the other hand, a transmission path clock signal on the digital transmission path is predetermined based on the transmission system in many cases and generally it has no relation to the sync signal of the television signal. In this manner, in a case where the sampling clock signal is independent of the transmission path clock signal, the sampling clock signal is usually aligned with the transmission path clock signal by, for example, transmitting a digitalized signal through a buffer memory. In this manner, alignment is established between the asynchronous clock signals. A buffer memory is provided on the receiving side for the same purpose. If the frequency of sampling clock signal on the transmission side does not coincide with that of sampling clock signal on the reception side, the buffer memory sometimes overflows or underflows.
For this reason, stuffing has been conventionally performed to coincide the transmission side sampling clock signal frequency with the reception side sampling clock signal frequency. However, in the conventional stuffing, since quasi-data frame near to a data frame on the transmission path is necessary, there is a problem in that the frequency of transmission path clock signal cannot be changed arbitrarily.
For this reason, a system in which the reception side sampling signal frequency can be coincided with the transmission side sampling signal frequency is disclosed in, for example, Japanese Examined Patent disclosure (JP-B2-Sho61-30456). The system will be described below with reference to FIG. 1. The system includes a transmitting unit 102, and a transmission path 104, and a receiving unit 106.
In the transmitting unit 102, a generating circuit 121 generates a sampling clock signal and a generating circuit 122 generates a transmission path clock signal necessary to transmit data onto the transmission path 104. A comparing circuit 123 comparing the sampling clock signal with the transmission path clock signal in accordance with a predetermined algorithm to output data indicative of a difference in frequency between the sampling clock signal and transmission path clock signals. A multiplexer 124 receives codes obtained by converting an analog signal into a digital signal and then by encoding the digital signal and the frequency difference data from the comparing circuit 123 and multiplexes them in response to the sampling clock signal. The multiplexed data is transmitted as a transmission signal on the transmission path 104 in response to the transmission path clock signal.
In the receiving unit 106, an extracting circuit 128 extracts the transmission path clock signal from the transmission signal on the transmission path 104. A pulse generating circuit 131 generates a sequence of write pulses. The sequence of write pulses is supplied to a buffer memory section 133. A demultiplexer 127 receives the transmission signal and demultiplexes the transmission signal into the digital data signal and the frequency difference signal. The data signal is supplied to the buffer memory section 133 and is stored therein in response to the write pulses from the pulse generating circuit 131.
A voltage controlled oscillating circuit (VCO) 130 generates a sampling signal control signal under control of a control unit 129. A pulse generating circuit 132 generates a sequence of read pulses as the reproduced sampling signal having the same frequency as that of the sampling signal control signal in response to the sampling signal control signal. The buffer memory section 133 reads out the stored digital data signal in response to the sequence of read pulses. A comparing circuit 134 receives the extracted transmission path clock signal from the extracting circuit 128 and the sampling signal control signal from the VCO 130 and determines a difference in frequency between the extracted transmission path clock signal and the sampling signal control signal. The control unit 129 controls the VCO 130 in accordance with the frequency difference signal from the demultiplexer 127 and the difference signal from the comparing circuit 134. In this manner, the control was performed such that the transmission side sampling signal frequency coincides with the reception side sampling signal frequency.
However, there is a problem in the conventional system in that the jitter of the reproduced sampling clock signal is great because quantization error is contained in the reproduced sampling clock signal.